diff options
| author | Ryan Harkin <ryan.harkin@linaro.org> | 2012-10-22 19:43:25 +0100 |
|---|---|---|
| committer | Ryan Harkin <ryan.harkin@linaro.org> | 2013-09-18 17:38:12 +0100 |
| commit | 29de2079d35b2ad169cb22e90946cd9a853d90c7 (patch) | |
| tree | cc49ccac96cd60baa43c6f23892467b916c3a4ee /ArmPkg | |
| parent | 94db469420a409947f1ec1f2d42269531aef8702 (diff) | |
VEA5: Fix problems booting linaro kernels
I copied the A15x2 BSP to the A5s and added in the init needed specifically for A5.
Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org>
Diffstat (limited to 'ArmPkg')
| -rw-r--r-- | ArmPkg/Drivers/ArmCpuLib/ArmCortexA5Lib/ArmCortexA5Lib.c | 5 | ||||
| -rw-r--r-- | ArmPkg/Include/Chipset/ArmCortexA5.h | 36 |
2 files changed, 5 insertions, 36 deletions
diff --git a/ArmPkg/Drivers/ArmCpuLib/ArmCortexA5Lib/ArmCortexA5Lib.c b/ArmPkg/Drivers/ArmCpuLib/ArmCortexA5Lib/ArmCortexA5Lib.c index 716a3d0a4..5dc3e6e94 100644 --- a/ArmPkg/Drivers/ArmCpuLib/ArmCortexA5Lib/ArmCortexA5Lib.c +++ b/ArmPkg/Drivers/ArmCpuLib/ArmCortexA5Lib/ArmCortexA5Lib.c @@ -15,6 +15,8 @@ #include <Base.h> #include <Library/ArmLib.h> #include <Library/ArmCpuLib.h> +#include <Library/ArmV7ArchTimerLib.h> +#include <Library/DebugLib.h> #include <Library/IoLib.h> #include <Library/PcdLib.h> @@ -33,9 +35,10 @@ ArmCpuSetup ( // If MPCore then Enable the SCU if (ArmIsMpCore()) { - // Signals the Cortex-A5 processor is taking part in coherency + // Turn on SMP coherency ArmSetAuxCrBit (A5_FEATURE_SMP); } + } diff --git a/ArmPkg/Include/Chipset/ArmCortexA5.h b/ArmPkg/Include/Chipset/ArmCortexA5.h index c9122709f..cba2eb3d9 100644 --- a/ArmPkg/Include/Chipset/ArmCortexA5.h +++ b/ArmPkg/Include/Chipset/ArmCortexA5.h @@ -1,6 +1,6 @@ /** @file - Copyright (c) 2011, ARM Limited. All rights reserved. + Copyright (c) 2012, ARM Limited. All rights reserved. This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License @@ -20,40 +20,6 @@ // // Cortex A5 feature bit definitions // -#define A5_FEATURE_PARITY (1<<9) -#define A5_FEATURE_AOW (1<<8) -#define A5_FEATURE_EXCL (1<<7) #define A5_FEATURE_SMP (1<<6) -#define A5_FEATURE_FOZ (1<<3) -#define A5_FEATURE_DPREF (1<<2) -#define A5_FEATURE_HINT (1<<1) -#define A5_FEATURE_FWD (1<<0) - -// -// Cortex A5 Watchdog -// -#define ARM_A5_WATCHDOG_REGION 0x600 - -#define ARM_A5_WATCHDOG_LOAD_REGISTER 0x20 -#define ARM_A5_WATCHDOG_CONTROL_REGISTER 0x28 - -#define ARM_A5_WATCHDOG_WATCHDOG_MODE (1 << 3) -#define ARM_A5_WATCHDOG_TIMER_MODE (0 << 3) -#define ARM_A5_WATCHDOG_SINGLE_SHOT (0 << 1) -#define ARM_A5_WATCHDOG_AUTORELOAD (1 << 1) -#define ARM_A5_WATCHDOG_ENABLE 1 - -// -// SCU register offsets & masks -// -#define A5_SCU_CONTROL_OFFSET 0x0 -#define A5_SCU_CONFIG_OFFSET 0x4 -#define A5_SCU_INVALL_OFFSET 0xC -#define A5_SCU_FILT_START_OFFSET 0x40 -#define AA5SCU_FILT_END_OFFSET 0x44 -#define A5_SCU_SACR_OFFSET 0x50 -#define A5_SCU_SSACR_OFFSET 0x54 - #endif - |