diff options
| author | Olivier Martin <olivier.martin@arm.com> | 2013-11-20 06:03:21 -0600 |
|---|---|---|
| committer | Steven Kinney <steven.kinney@linaro.org> | 2013-11-21 09:07:50 -0600 |
| commit | b94fabd981aa2437a8e2e1d41b4d8645bf62ca21 (patch) | |
| tree | 513b8322d81e6245dec4b9f65258bfb0a56c8841 | |
| parent | 2c5a8aed24170541fe7bf24e197c87b0e49d93d5 (diff) | |
ArmPkg/PL390Gic: Fixed setting of the Interrupt Processor Targets Registers when Uniprocessor
When running on a uniprocessor implementation, the ICDIPTRn registers are RAZ (Read as Zero).
So the previous assertion was not correct.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14798 6f19259b-4bc3-4df7-8a09-765794883524
Signed-off-by: Steven Kinney <steven.kinney@linaro.org>
| -rw-r--r-- | ArmPkg/Drivers/PL390Gic/PL390GicDxe.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/ArmPkg/Drivers/PL390Gic/PL390GicDxe.c b/ArmPkg/Drivers/PL390Gic/PL390GicDxe.c index ce96831a4..45a52be1c 100644 --- a/ArmPkg/Drivers/PL390Gic/PL390GicDxe.c +++ b/ArmPkg/Drivers/PL390Gic/PL390GicDxe.c @@ -378,12 +378,12 @@ InterruptDxeInitialize ( CpuTarget = MmioRead32 (PcdGet32 (PcdGicDistributorBase) + ARM_GIC_ICDIPTR);
// The CPU target is a bit field mapping each CPU to a GIC CPU Interface. This value
- // cannot be 0.
- ASSERT (CpuTarget != 0);
-
- // The 8 first Interrupt Processor Targets Registers are read-only
- for (Index = 8; Index < (mGicNumInterrupts / 4); Index++) {
- MmioWrite32 (PcdGet32 (PcdGicDistributorBase) + ARM_GIC_ICDIPTR + (Index * 4), CpuTarget);
+ // is 0 when we run on a uniprocessor platform. + if (CpuTarget != 0) { + // The 8 first Interrupt Processor Targets Registers are read-only + for (Index = 8; Index < (mGicNumInterrupts / 4); Index++) { + MmioWrite32 (PcdGet32 (PcdGicDistributorBase) + ARM_GIC_ICDIPTR + (Index * 4), CpuTarget); + } }
// Set binary point reg to 0x7 (no preemption)
|